? semiconductor components industries, llc, 2006 december, 2006 ? rev. 10 1 publication order number: mc74hc174a/d mc74hc174a hex d flip?flop with common clock and reset high?performance silicon?gate cmos the mc74hc174a is identical in pinout to the ls174. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device consists of six d flip?flops with common clock and reset inputs. each flip?flop is loaded with a low?to?high transition of the clock input. reset is asynchronous and active?low. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 162 fets or 40.5 equivalent gates ? pb?free packages are available* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com marking diagrams soic?16 d suffix case 751b tssop?16 dt suffix case 948f 1 16 pdip?16 n suffix case 648 1 16 1 16 1 16 mc74hc174an awlyywwg 1 16 hc174ag awlyww hc 174a alyw 1 16 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g = pb?free package = pb?free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 1 16 74hc174a alywg soeiaj?16 f suffix case 966 1 16
mc74hc174a http://onsemi.com 2 figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q4 d4 d5 q5 v cc clock q3 d3 d1 d0 q0 reset gnd q2 d2 q1 figure 2. logic diagram pin 16 = v cc pin 8 = gnd 3 4 6 11 13 14 2 5 7 10 12 15 d0 d1 d2 d3 d4 d5 q0 q1 q2 q3 q4 q5 clock 9 reset 1 data inputs noninverting outputs function table inputs output reset clock d q l x x l h h h h l l h l x no change h x no change design/value table design criteria value units internal gate count* 40.5 ea. internal gate propagation delay 1.5 ns internal gate power dissipation 5.0 w speed power product 0.0075 pj *equivalent to a two?input nand gate. ordering information device package shipping ? mc74hc174an pdip?16 500 units / rail mc74hc174ang pdip?16 (pb?free) 500 units / rail mc74hc174ad soic?16 48 units / rail MC74HC174ADG soic?16 (pb?free) 48 units / rail mc74hc174adr2 soic?16 2500 units / reel mc74hc174adr2g soic?16 (pb?free) 2500 units / reel mc74hc174adtr2 tssop?16* 2500 units / reel mc74hc174adtr2g tssop?16* 2500 units / reel mc74hc174afel soeiaj?16 2000 units / reel mc74hc174afelg soeiaj?16 (pb?free) 2000 units / reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free.
mc74hc174a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) 0.5 to 7.0 v v in dc input voltage (referenced to gnd) 1.5 to v cc 1.5 v v out dc output voltage (referenced to gnd) (note 1) 0.5 to v cc 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds pdip, soic, tssop 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 78 112 148 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v?0 @ 0.125 in. v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) 2000 100 500 v i latchup latchup performance above v cc and below gnd at 85 c (note 5) 300 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. i o absolute maximum rating must be observed. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to jesd22?c101?a. 5. tested to eia/jesd78. 6. for high frequency or heavy load considerations, see the on semic onductor high?speed cmos data book (dl129/d). recommended operating conditions symbol parameter min max unit ???? ???? v cc ????????????????????? ????????????????????? ????? ????? ???? ???? ??? ??? ???? ???? ????????????????????? ????????????????????? ????? ????? ???? ???? ??? ??? ???? ???? ????????????????????? ????????????????????? ????? ????? 55 ???? ???? 125 ??? ??? c ???? ? ?? ? ? ?? ? ???? t r , t f ????????????????????? ? ??????????????????? ? ? ??????????????????? ? ????????????????????? clock input rise and fall time (figure 4) v cc = 2.0 v v cc = 3.3 v v cc = 4.5 v v cc = 6.0 v ????? ? ??? ? ? ??? ? ????? 0 0 0 0 ???? ? ?? ? ? ?? ? ???? 1000 700 500 400 ??? ? ? ? ? ? ? ??? ns 7. unused inputs may not be left open. all inputs must be tied to a high? or low?logic input voltage level.
mc74hc174a http://onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 55 c to 25 c 85 c 125 c unit ???? ? ?? ? ???? v ih ????????? ? ??????? ? ????????? minimum high?level input voltage ????????? ? ??????? ? ????????? v out = 0.1 v or v cc ? 0.1 v |i out | 20 a ??? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ?????? 1.5 3.15 4.2 ??? ? ? ? ??? 1.5 3.15 4.2 ???? ? ?? ? ???? 1.5 3.15 4.2 ?? ?? ?? ???? ? ?? ? ???? v il ????????? ? ??????? ? ????????? maximum low?level input voltage ????????? ? ??????? ? ????????? v out = 0.1 v or v cc ? 0.1 v |i out | 20 a ??? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ?????? 0.5 1.35 1.8 ??? ? ? ? ??? 0.5 1.35 1.8 ???? ? ?? ? ???? 0.5 1.35 1.8 ?? ?? ?? ???? ? ?? ? ? ?? ? ???? v oh ????????? ? ??????? ? ? ??????? ? ????????? minimum high?level output voltage ????????? ? ??????? ? ? ??????? ? ????????? v in = v ih or v il |i out | 20 a ??? ? ? ? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ? ???? ? ?????? 1.9 4.4 5.9 ??? ? ? ? ? ? ? ??? 1.9 4.4 5.9 ???? ? ?? ? ? ?? ? ???? 1.9 4.4 5.9 ?? ?? ?? ?? ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 4.0 ma |i out | 5.2 ma ??? ? ? ? ??? 4.5 6.0 ?????? ? ???? ? ?????? 3.98 5.48 ??? ? ? ? ??? 3.84 5.34 ???? ? ?? ? ???? 3.7 5.2 ?? ?? ?? ???? ? ?? ? ???? v ol ????????? ? ??????? ? ????????? maximum low?level output voltage ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 20 a ??? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ?????? 0.1 0.1 0.1 ??? ? ? ? ??? 0.1 0.1 0.1 ???? ? ?? ? ???? 0.1 0.1 0.1 ?? ?? ?? ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 4.0 ma |i out | 5.2 ma ??? ? ? ? ??? 4.5 6.0 ?????? ? ???? ? ?????? 0.26 0.26 ??? ? ? ? ??? 0.33 0.33 ???? ? ?? ? ???? 0.4 0.4 ?? ?? ?? ???? ???? ????????? ????????? ????????? ????????? ??? ??? ?????? ?????? 0.1 ??? ??? 1.0 ???? ???? 1.0 ?? ?? a ???? ? ?? ? ???? i cc ????????? ? ??????? ? ????????? maximum quiescent supply current (per package) ????????? ? ??????? ? ????????? v in = v cc or gnd i out = 0 a ??? ? ? ? ??? 6.0 ?????? ? ???? ? ?????? 4.0 ??? ? ? ? ??? 40 ???? ? ?? ? ???? 160 ?? ?? ?? a 8. information on typical parametric values, along with high frequency or heavy load considerations, can be found in the on semi conductor high?speed cmos data book (dl129/d). ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) v cc guaranteed limit symbol parameter v 55 c to 25 c 85 c 125 c unit ???? ? ?? ? ???? f max ????????????????? ? ??????????????? ? ????????????????? maximum clock frequency (50% duty cycle) (figures 4 and 7) ??? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ?????? 6.0 30 35 ??? ? ? ? ??? 4.8 24 28 ???? ? ?? ? ???? 4.0 20 24 ?? ?? ?? ???? ? ?? ? ???? t plh t phl ????????????????? ? ??????????????? ? ????????????????? maximum propagation delay, clock to q (figures 5 and 7) ??? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ?????? 110 22 19 ??? ? ? ? ??? 140 28 24 ???? ? ?? ? ???? 165 33 28 ?? ?? ?? ???? ? ?? ? ???? t plh t phl ????????????????? ? ??????????????? ? ????????????????? maximum propagation delay, reset to q (figures 2 and 7) ??? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ?????? 110 21 19 ??? ? ? ? ??? 140 28 24 ???? ? ?? ? ???? 160 32 27 ?? ?? ?? ???? ? ?? ? ? ?? ? ???? t tlh t thl ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum output transition time, any output (figures 4 and 7) ??? ? ? ? ? ? ? ??? 2.0 4.5 6.0 ?????? ? ???? ? ? ???? ? ?????? 75 15 13 ??? ? ? ? ? ? ? ??? 95 19 16 ???? ? ?? ? ? ?? ? ???? 110 22 19 ?? ?? ?? ?? ???? ???? ????????????????? ????????????????? ??? ??? ?????? ?????? ??? ??? ???? ???? ?? ?? typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance, per enabled output (note 10) 62 pf 10. used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see the on semiconductor high?speed cmos data book (dl129/d).
mc74hc174a http://onsemi.com 5 timing requirements (c l = 50 pf, input t r = t f = 6.0 ns) guaranteed limit v cc 55 c to 25 c 85 c 125 c symbol parameter figure v min max min max min max unit ???? ? ?? ? ???? t su ????????????? ? ??????????? ? ????????????? minimum setup time, data to clock ??? ? ? ? ??? 6 ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 50 10 9.0 ??? ? ? ? ??? ??? ? ? ? ??? 65 13 11 ??? ? ? ? ??? ??? ? ? ? ??? 75 15 13 ??? ? ? ? ??? ?? ?? ?? ns ???? ? ?? ? ???? t h ????????????? ? ??????????? ? ????????????? minimum hold time, clock to data ??? ? ? ? ??? 6 ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ?? ?? ?? ns ???? ? ?? ? ? ?? ? ???? t rec ????????????? ? ??????????? ? ? ??????????? ? ????????????? minimum recovery time, reset inactive to clock ??? ? ? ? ? ? ? ??? 5 ??? ? ? ? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ? ? ? ??? ??? ? ? ? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ? ? ? ??? ??? ? ? ? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ? ? ? ??? ?? ?? ?? ?? ns ???? ? ?? ? ???? t w ????????????? ? ??????????? ? ????????????? minimum pulse width, clock ??? ? ? ? ??? 4 ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 75 15 13 ??? ? ? ? ??? ??? ? ? ? ??? 95 19 16 ??? ? ? ? ??? ??? ? ? ? ??? 110 22 19 ??? ? ? ? ??? ?? ?? ?? ns ???? ? ?? ? ???? t w ????????????? ? ??????????? ? ????????????? minimum pulse width, reset ??? ? ? ? ??? 5 ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 75 15 13 ??? ? ? ? ??? ??? ? ? ? ??? 95 19 16 ??? ? ? ? ??? ??? ? ? ? ??? 110 22 19 ??? ? ? ? ??? ?? ?? ?? ns ???? ? ?? ? ???? t r , t f ????????????? ? ??????????? ? ????????????? maximum input rise and fall times ??? ? ? ? ??? 4 ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? ??? ? ? ? ??? 1000 500 400 ??? ? ? ? ??? ??? ? ? ? ??? 1000 500 400 ??? ? ? ? ??? ??? ? ? ? ??? 1000 500 400 ?? ?? ?? figure 3. expanded logic diagram c q d r c q d r c q d r c q d r c q d r
mc74hc174a http://onsemi.com 6 50% v cc gnd v cc gnd 50% clock q reset t phl figure 4. switching waveform 50% data clock v cc v cc gnd figure 5. switching waveform valid gnd t su t h 1/f max clock q t r t f v cc gnd 90% 50% 10% 90% 50% 10% t plh t phl t tlh t thl t w *includes all probe and jig capacitance c l * test point device under test output figure 6. switching waveform figure 7. test circuit t w t rec 50%
mc74hc174a http://onsemi.com 7 package dimensions pdip?16 n suffix case 648?08 issue t soic?16 d suffix case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x
mc74hc174a http://onsemi.com 8 package dimensions tssop?16 dt suffix case 948f?01 issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint
mc74hc174a http://onsemi.com 9 package dimensions soeiaj?16 f suffix case 966?01 issue a h e a 1 dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 0.78 ??? 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc74hc174a/d publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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